Dolphin ECC MCA Specification Nov78

This document is the Dolphin ECC MCA Functional Specification Revision 3, dated November 3, 1978. It describes a Macro Cell Array (MCA) designed to implement Single Error Correction / Double Error Detection (SEC/DED) across all RAMs and Busses within the Dolphin System.

Key aspects of the specification include:

• Core Function: It uses a Hamming code with an overall parity bit to provide SEC/DED for a 36-bit data word. This results in a 43-bit protected word, comprising 36 data bits and 7 check bits.

• Modes of Operation: The ECC chip operates in two main modes:

  • Generation Mode: Supplies the 7 check bits for a 36-bit data word.
  • Checking Mode: Takes in all 43 bits, provides error detection signals, and locates any single error. (Error correction itself is handled by associated hardware, not the chip).

• Parity Support: Provision is also made for generating and checking parity on 18-bit half words and 9-bit quarter words.

• Design Goals: To provide SEC/DED for all Dolphin RAMs and Busses using a single code and chip design, ensure fast checks, simplify syndrome decoding, and allow syndrome outputs to drive a bus.
• Code Assignment & Slicing: The document details the specific code assignment, including support for "bit sliced" data paths (4-bit, 8-bit, and 6-bit slices) common in the Dolphin system. It includes methods for re-mapping syndromes for easier decoding and explains how check bits are complemented to ensure robust error detection (e.g., preventing an all-zero word from appearing "good").
• Limitations: In 6-bit slice mode, check bit errors yield zero syndromes, meaning check bits cannot be corrected.
• Functions & Control: Various operational modes (e.g., normal, diagnostic, check bit generation, syndrome output, half/quarter word parity) are controlled via a Diagnostic Status Register.
• Pincuts: The document outlines the functions of various pins, including data inputs, check bit I/O, syndrome I/O, parity I/O, error signals, and control inputs.