Dolphin Console Functional Specification Sep78

Order Number: XX-08F47-25

This document is a Functional Specification for the Dolphin Console, marked "COMPANY CONFIDENTIAL" and dated September 1978. It outlines the design and operational requirements for a critical system component, explicitly stating that the information is subject to change and not a binding commitment.

Key aspects of the Dolphin Console:

  1. Purpose & Role: It serves as a TOPS20 Operating System terminal, a System Console (for bootstrapping, power-fail restart, system initialization, and software updates), and a Diagnostic Console. It can access system registers and buses via a special diagnostic bus, controlled by keyboard commands.

  2. Architecture (Primary Strategy):

    • Based on an F-11 Microcomputer with 96K bytes of RAM and 16K bytes of ROM (for bootstrap, monitor, diagnostics, and console routines).
    • Utilizes the PDT/TOBY/UNIBUS as the primary micro-system, aiming for flexibility and cost-effectiveness. A secondary strategy using an 1134A is a backup if the primary is delayed or cancelled.
    • The "TOBY" machine is a single-board computer, designed for high-performance PDP-11 Instruction Set Processing (ISP) in intelligent terminals, integrating with a VT100 terminal for the human interface.
    • Includes 5 RS-232C serial line interfaces and a DecTape II for mass storage of diagnostic programs and software updates.
  3. Core Components & Functions:

    • Dolphin Clock and Distribution: Provides enhanced clock control, including burst, single-step, start/stop/continue, and independent clocking for memory and CPU. Features battery backup for data integrity.
    • Dolphin Bus Recorder: Acts both as a bus activity recorder (latching 62-wire bus information, logging ECC errors, stopping on detected errors) and as Dolphin Random Access Memory for diagnostics and system initialization.
    • Dolphin Bus Interface: Allows the PDP11 CPU to interact with the Dolphin bus for diagnostics, data transfer, and acting as a pseudo Dolphin CPU.
    • Dolphin Time of Day Clock: Battery-powered (runs for at least 100 hours without AC) 32-bit clock.
    • Diagnostic Logic: An important part of machine configuration, it allows for serial communication with Micro Cell Arrays (MCAs) on modules for module selection, data extraction/insertion, function transmission, and clock control.
    • Power and Environmental Logic: Provides comprehensive monitoring of fans, air movement, supply voltages, ambient and internal temperatures (with soft/hard limits for warnings/shutdowns), and controls power sequencing and emergency shutdown. This logic, controlled by an 8085 micro, includes programmed intelligence for making decisions about system health.
    • Dolphin Bus Arbitrator: Manages access to the Dolphin bus, with dual arbitrators for high availability.
    • Terminals: Defines the use of 8 Serial Line Units (SLUs) for connections like hard copy (LA120), real-time display (VT100), modems for KLINIK, and interprocessor communication.
    • Real-Time Display: Provides an operator interface for real-time information on machine modes, states, program counter, memory data, and cache status.
  4. Design Goals & Requirements:

    • Cost: Target transfer cost of $1,500 or less for the core microsystem.
    • Reliability: MTBF goals of >= 5000 hours for PDT11 + Hex modules, and >= 20000 hours for Hex modules (excluding electromechanical devices). MTTR goal of 2 hours, and MTTD goal of 45 minutes or less (for initial diagnosis).
    • Packaging: Desirable in a compact terminal enclosure (VT100) with internal logic fitting on 2-3 extended hex modules.
    • Performance: Microprocessor instruction set equivalent to an 1134A, executing at a minimum of 0.2 MIPS.
    • Availability: Desired by July 1979, required by October 1979.
    • Compliance: Must meet DMT, PMT, UL, CSA, and IEC specifications.

The document includes a Table of Contents, a list of development personnel, identified project risks (e.g., ensuring Toby project funding and schedule adherence), and a list of applicable supporting documents. Appendices include a block diagram and a project schedule.

XX-08F47-25
September 1978
33 pages
Quality

Original
1.7MB

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