Dolphin Clocking Control and Distribution Spec Oct78

This document details the control and distribution specification for Dolphin processor clocking, emphasizing architecture, functionality, and timing precision.

Key aspects include:

1. Clock Sources and Frequencies: Dolphin systems can use an internal VFO (Variable Frequency Oscillator) on the console or an external oscillator for multi-processor configurations. The nominal clock frequency is 60 MHz, from which the 30 MHz Dolphin bus clock is derived by dividing by two.
2. Phase Synchronization: Crucial for multi-processor systems, phase information is provided by the external oscillator and maintained by clock distribution logic. Clocks are alternately labeled "phase A" and "phase B" to ensure synchronous operation across bus repeaters.
3. Distribution Architecture: Clocks are distributed through a hierarchical system of Clock Distribution MCAs (Module Control Adapters) in a tree structure. A master VFO feeds the Clock Control MCA, which then distributes to a first level of MCAs (Level I) that control overall clocking rates. These, in turn, feed a second level of MCAs (Level II) that provide individual clocking rates to specific logic sections and modules.
4. Control Functions: The system supports various clock control functions including turning clocks ON/OFF, performing a HALF STEP (advancing the clock by half a cycle), BURSTing a specified number of clocks, and selecting the oscillator source (internal or external).
5. Frequency Adjustment: The master VFO's frequency can be varied from 50 to 70 MHz in 0.5 MHz steps for diagnostic and margining purposes. Clock frequencies can also be altered by dividing the oscillator's frequency by 2, 4, or 6.
6. Clock Stopping and Error Reporting: Multiple methods exist to stop clocks, including preventing output on specific phases, using external strobed stop/field input signals, or via IIL logic for independent sections. The system incorporates parity checks on clock rate inputs and asserts error flags if issues are detected, which must be explicitly cleared.
7. Timing Precision (Skew): The document provides detailed specifications for clock "skew" across different paths and loads (e.g., same board, different modules, memory arrays), highlighting the critical importance of precise timing in the system's design.

In essence, the Dolphin clocking system is designed for robust and synchronized clock distribution, particularly in complex multi-processor environments, with extensive controls for frequency, phasing, and diagnostics.