minnow Schems

This document is a comprehensive set of schematic diagrams detailing the hardware design of the MINNOW ALU (Arithmetic Logic Unit) system. It illustrates the complete data paths, control logic, memory architecture, and input/output interfaces.

Key aspects of the system include:

1. ALU and Data Paths: Central to the design is an Arithmetic Logic Unit (ALU) with an associated Shifter, supported by various registers (e.g., RAMFILE, general-purpose register files) and pipeline registers, indicating a pipelined architecture.
2. Memory Subsystem: The system incorporates multiple memory types: a RAMFILE, a Page Table, Fast Memory, and a Code Workspace, in addition to a larger main memory referred to as "Minnow Mem" (MOS Array).
3. Control Logic: Operations are orchestrated by a 2910 Sequencer, a Control Read-Only Memory (CROM), and various control logic blocks, including Programmable Array Logic (PALs) for decoding and signal generation. A Microsequencer and Microcode Storage are detailed, suggesting a microcoded control approach. Processor flags and status registers provide operational feedback.
4. Input/Output (I/O): The document details I/O line drivers and receivers, I/O priority, and interrupt control mechanisms. A significant portion is dedicated to a Disk Control subsystem, outlining its registers, data separation, write control, and interface to memory.
5. Interconnect and Support: Various buses (e.g., CON Bus, D Bus, MEN Bus, Port Bus) facilitate data and control signal transfer between components. Essential support functions such as Clock Generation, power distribution ("Power Bodies"), and physical connectors are also documented.

Overall, the document provides a granular view of a custom processor's hardware implementation, encompassing core processing, complex memory management, disk I/O capabilities, and a microcoded, pipelined control structure.