KS10-Based DECSYSTEM-2020

This technical manual, intended for Digital Equipment Corporation Field Service personnel, provides a comprehensive overview of the KS10-based DECSYSTEM-2020. This system is a low-end mainframe computer that combines a microprogrammed architecture with low-power/high-density LS/TTL circuitry, supporting both TOPS-10 and TOPS-20 operating systems.

The document covers the system's physical description, including its housing in a single-width high-boy cabinet, the KS10PA card cage, and the BA11-K drawer for I/O peripheral controllers. It details the KS10 processor's architecture, which includes a 512-word virtual-address cache, fast general-purpose registers, parity checking, and a 300 ns micro-instruction cycle time. The memory system utilizes MOS memory modules (128K to 512K words) with error correction and detection capabilities.

Key operational aspects include the KS10 (backplane) bus, a synchronous multiplexed 2-cycle bus that facilitates data transfer, I/O register operations, and priority interrupt handling between the processor, memory, console, and Unibus adapters (UBAs). The manual outlines system timing, bus arbitration, and various bus operations such as memory read/write and I/O register transfers. It also describes the console's function, driven by an 8080 microprocessor for system control, diagnostics, and remote diagnosis (KLINIK line).

Programming information highlights differences between KS10 and KL10 systems, such as public mode not being implemented, specific addressing schemes, modified interrupt handling, and a new KS10 I/O instruction set. Detailed technical descriptions are provided for the microcontroller (microword formats, dispatch logic, control RAM, booting/diagnosis), data path execution (arithmetic unit, RAM file, program flags), data path memory (paging, cache, error logic, priority interrupt), and the KS10 power system. An appendix offers a summary of the Unibus interface and its operations.