KS702

This document is a detailed "Table of Contents" and "Cross Reference Listing" for the KS10 Microcode V124, dated July 27, 1984. It outlines the structure and functionality of the microcode, including:

• Revision History: A log of changes made to the microcode over time, detailing fixes, updates, and enhancements.
• How to Read the Microcode: Explanations of field definitions, label definitions, comments, microinstruction definitions, continuation rules, macros (including register transfer, memory, time control, SCAD, skips, dispatch, and super macros), and pseudo-operators.
• Conditional Assembly Definitions: Parameters and options for assembling different versions of the microcode, such as for simulator vs. real hardware, basic vs. full instruction sets, and paging support.
• 2901 Register Usage: A table describing the purpose of various registers like PC, HR, AR, ARX, BR, BRX, EBR, UBR, MASK, FLG, PI, XWD1, TO, and T1.
• Microcode Fields: Detailed breakdowns of microcode fields for listing format, datapath chip, RAM file address and D-bus, parity generation & half-word control, and special functions (SPEC, SKIP, TIME CONTROL, RANDOM CONTROL BITS, NUMBER FIELD).
• Dispatch ROM Definitions: Categories of dispatch operations, including operand fetch modes, store results options, floating-point operations, and various dispatch addresses.
• Macro Definitions: Extensive listings of macros categorized by function (Data Path Chip - General, Q, Misc.; Store in AC; Microcode Work Space; Memory Control; VMA; SCAD, SC, FE Logic; Data Path Field Control; Shift Path Control; Special Functions; PC Flags; Page Fail Flags; Single Skips; Special Dispatch Macros).
• Dispatch ROM Macros: Definitions for various instruction execution paths, such as Power Up Sequence, Instruction Loop (Start Next Instruction, Fetch Arguments, Store Answers), and groups of instructions (Move, Exch, Halfword, DMOVE, Boolean, Rotates and Logical Shifts, Test, Compare, Arithmetic Skips, Conditional Jumps, AC Decode Jumps, Extended Addressing Instructions, XCT, Stack, Subroutine Call/Return, Illegal Instructions and UUO's, Arithmetic, Byte Group, BLT, UBABLT, Floating Point, Extend).
• Extended Microcode Sections: Specific sections for Power Up Sequence, Instruction Loop, Move/Exch/Halfword/DMOVE/Boolean/Rotate/Test/Compare groups, Arithmetic/Skips/Jumps, AC Decode, Extended Addressing Instructions, XCT, Stack Instructions, Subroutine Call/Return, Illegal Instructions and UUO's, Arithmetic operations (ADD, SUB, MUL, DIV, DADD, DSUB, DMUL, IDIV, etc.), Byte Group operations, BLT, UBABLT, Floating Point operations, EXTEND functions (Dispatch ROM Entries, Instruction Set Decoding, Move String, Compare String, Decimal/Binary Conversion, Edit, Extend Subroutines), Traps, Internal Devices (EBR & UBR, KL Paging Registers, Timer Control, WRTIME & RDTIME, WRINT & RDINT, ROPI & WRPI, Subroutines), Priority Interrupts, External IO Instructions, Small Subroutines, Undefined IO Instructions, UMOVE and UMOVEM, Write Halt Status Block, and Page Fail Refil Logic.

The document serves as a comprehensive reference for understanding the KS10 Microcode, detailing its internal architecture, instruction set, and operational logic.