TOPS-10-20 Sales Training Student Guide

This document is a TOPS-10/20 Sales Training Student Guide for Digital Equipment Corporation, marked "For Internal Use Only." It provides a detailed technical overview of the KL processor architecture and its various subsystems, along with the historical evolution of the TOPS-10/20 operating systems.

Key areas covered include:

1. KL Architecture: Details the evolution of Digital's 36-bit CPU family (PDP-6, KA, KI, KL), highlighting the KL processor's microprogrammed ECL implementation, cache memory, expanded memory, and integrated front-end/I/O. A primary design goal was software compatibility and significant price/performance improvements across generations, with the KL achieving 1.8 MIPS, a substantial increase over its predecessors.

2. The E-Box (Execution Box): This is the core instruction execution unit of the KL processor. It leverages microprogramming for flexibility, enabling the same hardware to support both TOPS-10 and TOPS-20, facilitate engineering changes, and enhance virtual memory and cache operations. The E-Box features USER and EXECUTIVE processor modes for system integrity and includes general-purpose registers and various timing/accounting meters.

3. The Memory Subsystem: Managed by the M-Box, which handles all memory requests, paging (address translation), and the integrated cache. The KL supports both external (via DMA, up to 4096K words for TOPS-10) and internal (MOS/core, up to 1.5 million words) memory. A sophisticated cache memory significantly reduces instruction execution time by storing frequently accessed data, and hardware-implemented memory mapping enables virtual memory, multi-user support, and protection between users.

4. The Front-End Subsystem: A PDP-11-based minicomputer acts as a front-end, providing console functions, remote/local maintenance, and support for unit record equipment. It interfaces with the KL via a dedicated DTE (Digital Ten-to-Eleven) interface and features KLINIK for advanced remote diagnostics.

5. The I/O Subsystem: Describes how peripherals connect to the KL using Digital's "BUS" architecture, including four main external buses:

   • Multiplexed I/O Bus: For TOPS-10, supporting low-speed devices like printers and card readers.
   • Memory Bus Subsystem: Supports external memory connection (TOPS-10 only) with DMA for high-speed data transfer.
   • MASSBUS: Connects high-speed peripherals (disks, tapes) via RH20 controllers, featuring a "silo" buffer for efficient block transfers and supporting overlapped I/O.
   • UNIBUS: Connects a wide range of peripheral and communication equipment, utilizing the DTE interface with distinct privileged and restricted modes for system control and user device access.

6. TOPS-10 History and Evolution: The foreword and a detailed table illustrate the evolution of the TOPS-10 Monitor from the early 1960s (PDP-1, PDP-6 "Gentlemen's Timesharing") to the KL10 (1975). This includes expanded functionality in areas like protection (single segment to virtual machine), program swapping (core shuffling to demand paging), resource allocation, scheduling, file management, command control, batch processing, terminal handling (including DECnet), and multiprocessing.

In essence, the document is a comprehensive guide for sales personnel to understand the technical foundations, capabilities, and historical context of the Digital KL processor supporting the TOPS-10/20 operating systems.