DTR01/DR01 Channel Interface Subsystem

This technical manual describes the DTR01/DR01 Channel Interface Subsystem, a high-speed channel port system designed by Digital Equipment Corporation. Its primary function is to facilitate high-speed block data transfers between user devices and the main memory (KL10-B, C, D, or E processors). Additionally, it enables high-speed interprocessor links between KL10 systems, or between a KL10 and a PDP-11 or PDP-11/70 system.

Key features include high-speed block transfers, an expanded interface that builds upon the DR11-B (offering switch-selectable word or byte data transfer, optional parity checking, and user-defined status and function bits), and support for a maximum of eight channel interfaces.

The manual provides detailed specifications covering mechanical aspects (various cabinet and unit configurations, dimensions, weight), electrical characteristics (voltage, current, power, BTU), operational parameters (e.g., 1 megabyte/second max. word mode transfer rate, cable lengths), and environmental conditions.

Installation procedures are thoroughly outlined, including verifying CPU revision levels, installing the RH20 Massbus controller, performing clock deskew, running diagnostic tests, user interface cabling, grounding, power-up checks, device number selection via DIP switches (for drive address, word/byte mode, and input parity inhibit), and adjusting the maximum transfer rate to match system bandwidth.

Operation and programming guidance details the protocol for host-to-device communication, focusing on the use of seven programmable registers within the DR01-CL interface unit. These registers are accessed using DATAO and DATAI instructions from the CPU. The manual describes single-word transfer mechanisms and redefines specific register bits for interprocessor link configurations.

Maintenance information covers general preventive checks and corrective actions, recommending the use of diagnostic tools like the DFDRA.A10 diagnostic and console commands for accessing internal and external registers. Appendices provide further details on linking procedures for DR01/DR11-B and DR01/DR01 configurations, as well as comprehensive user interface specifications, including signal lists and timing diagrams.