A Document On The KI10

This document provides a comprehensive overview of the KI10 system, based on a 1973 seminar. It details the KI10's hardware and software architecture, emphasizing its virtual memory capabilities, double-precision floating-point hardware, and large address space, which supports demand paging through the TOPS10 monitor.

Key hardware features include support for up to 4MB of 36-bit memory, a 256K 36-bit user virtual address space, and four distinct processor modes (Kernel, Supervisor, Concealed, and Public) designed for multi-user protection. The KI10 also incorporates instruction pipelining with overlapped memory fetches and utilizes different general register sets for user and executive programs. Its instruction set of 378 commands includes multi-level indirect addressing, immediate mode addressing, fixed-floating conversions, and independent trap handling.

A central theme is the KI10's paging mechanism, which segments programs into 512-word pages. Virtual addresses are translated to physical memory locations using a page map (also referred to as associative memory, paging box, or relocation hardware). The 18-bit virtual address is divided into 9-bit page and 9-bit offset fields. This translation is accelerated by a 32-register associative memory cache, reducing the need for direct lookups in the User Page Map Page (UPMP) or Executive Page Map Page (EPMP). Page faults can occur due to protection violations, non-existent pages, or cache misses.

The four processor modes provide granular control over memory access and system functions. Kernel mode handles critical system operations like interrupts and I/O, Supervisor mode manages single-user functions, Concealed mode protects proprietary programs, and Public mode is for standard user execution. Write protection can be dynamically altered, primarily by Kernel mode.

The document also highlights significant differences in the KI10's instruction set compared to its predecessor, the KA10, particularly in stack, byte, and shifting operations, conversion instructions, and an increased precision (62 bits) for double-precision floating-point arithmetic. Detailed explanations are provided for double-move instructions, arithmetic testing, program control (e.g., JSR, JSP, PUSHJ, POPJ), PC flags, and Unimplemented User Operations (UUOs).

Memory management is further optimized through overlapping read cycles across different memory types (fast, slow) and pipelining of memory control subroutines. A prefetch feature allows the processor to fetch subsequent instructions while the current one is still executing. The monitor's role in leveraging these features for memory referencing, managing "exec virtual memory" (EVM) for I/O and swapping of non-current users, and maintaining physical page tables is also described.

Finally, the document includes a section on the KI10 console, detailing its lights, switches, and functions for system status indication, addressing, and debugging, covering aspects like page map violation indicators and operational modes.