This document, the "NIA-XX Interface Specification," details the interface between an NIA (Network Interface Adapter) and a proposed Ethernet CSMA/CD Communication Network.
The primary purpose is to describe how a host "port" interacts with the NIA's link/packet buffers for data transfer and communication. The interface is signal-based, with the port acting in a master/slave relationship, controlling all data traffic and PLI (Port/Link Interface) functions.
Key aspects covered in the specification include:
- PLI Interface Signals: A comprehensive list of signals for data transfer (8-bit), control (e.g., SELECT, PLI/LINK CONTROL), and attention/status (e.g., RCVR ATTENTION, XMTR ATTENTION, END OF FRAME), along with parity lines and timing specifications.
- Buffer Management: Details on transmit and receive buffers, their formats, and how they are managed (e.g., Free Buffer List, Used Buffer List, Receive Buffer Read Address Register) for efficient handling of incoming and outgoing frames.
- Registers: Descriptions of various registers, including Transmit Status Register (for transmission success/errors), Receive Status Register (for incoming frame integrity and buffer status), Link Control Register (for configuring link behavior like promiscuous mode, loopback, and CRC), Physical Address ROM/Register (for MAC addressing), Time Domain Reflectometry (TDR) Register (for diagnostics), and Collision Test Register.
- Frame Handling: Specifications for frame formats in both transmit and receive paths, parity checking mechanisms, and procedures for transmitting multicast frames and receiving loopback type frames.
- Operational Flow: Flow diagrams illustrating the sequence of operations for both receiving and transmitting frames.
- Physical Layer: Details on the transceiver cable connectors and their pin assignments.
In essence, the document provides the technical blueprint for the hardware and software interface, enabling a host system to effectively send and receive data over an Ethernet network via the NIA.