Jupiter DevelopmentPlan Sep80

Order Number: XX-90B15-20

This document, the "JUPITER SYSTEM DEVELOPMENT PLAN" dated September 16, 1980, is a confidential internal plan from Digital Equipment Corporation (Digital/DEC) outlining the development of a new computer system called JUPITER.

Primary Goals: The JUPITER project's top priorities are the earliest possible time to market, achieving high performance (5 to 7.5 times the KL10E, with a guaranteed minimum of 5.0 times, and 5 times for FORTRAN with an Arithmetic Processing Accelerator or APA), lowest cost of ownership, and coexistence with VAX systems. Secondary goals include sufficient microcode address space for future enhancements, comprehensive error detection with logging, and improved remote diagnostic capabilities.

System Architecture & Technology: JUPITER is designed as a modular CPU cluster that will serve as an upgrade path for existing TOPS-10 and TOPS-20 customers, initially supporting the TOPS-20 multi-terminal, multi-language operating system. The system will initially be MASSBUS-based, with a future transition to CI-based configurations for multi-system support. Key hardware components include:

  • IBOX (Instruction Box): Responsible for pre-fetching instructions and operands to boost speed.
  • EBOX (Execution Box): Performs core computations under wide microcode control and manages memory stores.
  • MBOX (Memory Box): The central memory block containing cache, paging hardware, and main memory (64K MOS memory chips, expandable to 4 million words initially).
  • APA (Arithmetic Processing Accelerator): Dedicated hardware to speed up floating-point and integer operations.
  • PORT: A microprogrammed I/O processor handling data repacking, command processing, and interrupt processing for various interfaces (ICCS, MASSBUS, UNIBUS, IBM BLOCK MUX, though some advanced I/O will not be available at first ship). The system utilizes advanced technologies for its time, such as ECL 100K MSI/SSI chips, 1K and 4K ECL RAMs, multilayer backplanes, and switching regulator power supplies, all air-cooled.

Development & Schedule: The development process is structured into breadboard, prototype, and pilot phases, with early involvement from manufacturing, customer service, and system qualification teams. The aggressive schedule targets CPU power-on by January/April 1981, system login by June 1981/January 1982, field testing by February/November 1982, and First Revenue Ship (FRS) by August 1982 (optimistic 50% date) or July 1983 (realistic 90% date). Extensive use of Computer-Aided Design (CAD) tools is planned for hardware design and simulation. TOPS-20 will be released with the initial JUPITER systems, with TOPS-10 following about a year later.

System Realization Strategies:

  • Manufacturing: Aims for efficient, cost-effective production of a reliable product, requiring a significant capital expenditure of approximately $1.8 million for new technology manufacturing equipment.
  • Qualification: Involves rigorous testing to ensure the system meets design specifications, cost goals, reliability (Mean Time Between Failure/Mean Time To Repair), and compliance with international and FCC regulations.
  • Diagnostics: A comprehensive strategy for fault detection, isolation, and system recovery. It targets >99% fault detection, isolating issues to one or two boards, and utilizes an instruction retry technique to reduce system crashes.
  • Customer Service: Focuses on modular replacement (Field Replaceable Units), leveraging the instruction retry mechanism, and a structured call handling sequence (Service Dispatcher, Assistance Center, Specialist, Branch Support) to achieve high system availability (no more than 1% monthly unavailability or 7.2 hours).

Risks & Dependencies: Key risks identified include challenges in sourcing multi-signal layer PC boards, potential schedule delays due to complex interdependencies and component availability (1K/4K ECL RAMs), resource conflicts with other Digital programs (e.g., VENUS), high transfer costs linked to new technologies, and compliance with evolving FCC regulations on radio frequency emissions. The project is heavily dependent on the successful development of sophisticated CAD software and the performance of various internal Digital groups.

Cost: The total estimated engineering development expense is approximately $12.7 million, covering CAD tools, memory, packaging, system design, technology, materials, TOPS-20, and communications software. The manufacturing cost for a basic JUPITER cluster is estimated at $60,743 (based on 1982 projections).

XX-90B15-20
March 1980
51 pages
Quality

Original
2.2MB

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