uhler Impressions from a visit to Foonly 19830719

This interoffice memo, dated July 19, 1983, by Mike Uhler, summarizes a visit to Foonly to discuss upgrading their F1 processor to support extended addressing and explore a potential business relationship with Digital (DEC). The memo outlines Uhler's impressions of the existing F1, Foonly's upgrade proposal, and the project's chances of success.

The Foonly F1 is a pipelined PDP-10 processor, built around 1978, using 10K ECL logic with a 90ns cycle time. It currently lacks extended addressing, functioning as a KL10 model A (emulating a KA10). Its multi-stage pipeline includes a Prefetch unit, IBOX (instruction/operand fetch, address generation), EBOX (instruction execution, memory management), and MBOX (page table, cache, memory controller, I/O interface).

Foonly proposes upgrading the F1 to the F1B, primarily adding extended addressing. This largely involves changes to the IBOX address generation logic, plus significant microcode modifications for KL instructions, memory management, and PXCT. While Foonly's Dave Poole demonstrates understanding of the necessary changes, the success of the project hinges on receiving external consulting (especially on extended addressing) without being bogged down by DEC's bureaucratic development processes.

Foonly's Overall Plan for F1B: The plan leverages Foonly's existing F1 prototype, the public-domain SCALD CAD system (including S-1 supercomputer design information for ECL 10K circuits, packaging, and power supply), and their Console Computer system.

Key F1B modifications include:

• Memory: Adapting the F1's memory interface to use Foonly's standard 16k/256k MOS dynamic RAM boards, significantly boosting speed by reducing cache miss penalties.
• I/O: Utilizing Foonly's extensive FBUS I/O controllers for various peripherals (disks, tape, Ethernet, ARPAnet), with four controllers to ensure high bandwidth.
• Microcode/Hardware: Expanding microcode memory from 2K to 8K and history memories to 1K entries using new ECL RAMs. Implementing KL Pager and specific KL instructions, with previous work on the F4 providing models.
• Hardware Details: The system will use wire-wrapped panels (similar to the S-1 project) for initial versions, with potential future conversion to PC boards. DEC is expected to handle enclosure, metalwork, and power supply engineering to meet regulatory requirements.
• Timeline: Foonly aims for delivery of the first test site system in 12 months, with logic changes and layout done in 4 months, two pre-production units built in the following 2 months, and production units checked out by the 12th month.

Maintenance: Foonly proposes an "Instant Expert Service" (IES) model, using remote connectivity via a Console Computer to allow expert diagnosis and initial problem resolution by Support Center personnel. This system includes extensive debugging aids like history memories and configurable logic analyzers. Field service personnel would receive minimal training, operating under remote expert supervision to replace parts on-site.

Uhler notes that the existence of a running F1 machine improves the project's chances. He believes Dave Poole has a reasonable probability of success within the indicated timeframe, provided he receives necessary consulting and is not hindered by Digital's standard hardware development processes.