KA10 EngineeringDrawings

This document, titled "PDP-10 Processor Layout," appears to be a comprehensive set of engineering diagrams or schematics for a Digital Equipment Corporation (DEC) PDP-10 computer.

The document includes detailed circuit diagrams and logic flow for various components and operations within the PDP-10 processor, such as:

• Arithmetic Operations: Adder control, levels, and registers (AR, MQ).
• Data Transfer and Memory: Block transfers, memory address interface, memory bus data interface, fast memory access, and memory control.
• Control and Instruction Processing: AR control pulses, AR control levels, instruction and address cycles, IR decoding, execution cycle, fetch cycle, store cycle, and basic instruction flow diagrams for various operations like DIV, FMP, FADD, FMOV, FMPY, MUL, ROTATE, SKIP, JUMP, CAM, PUSH, POP, PRDT, PCT, FOD, FADD, FSB, and UFA.
• Registers and Flags: AR register, MQ register, arithmetic flags, program counter register, shift count register, floating exponent register, and floating exponent status register.
• Input/Output and Interrupts: I/O bus control, I/O selection, priority interrupt, PTP (paper tape punch) control, PTR (paper tape reader) control, TTY (teletype) control, and console switch connections.
• Module Utilization: Extensive tables detailing the utilization of various modules across different PDP-10 panels, indicating signals, levels, and connections.

The document uses a mix of schematic symbols, signal names (e.g., AR, MQ, PC, IR, FMA), and notes to describe the logical and physical interconnections. Many pages include notes indicating that certain modules are optional, and there are occasional references to resistor wiring and panel bussing. Overall, it serves as a technical blueprint for the PDP-10's internal architecture and functionality.