M-1099 Apr61

This document describes the Type 14 Memory Expansion for the PDP-1 computer, which increases the total memory capacity to 32K words (compared to Type 11's 16K words).

The core of this expansion is a memory switching mechanism that divides the total memory into eight 4096-word modules. Programmers control this switching using the jfd Y (jump field) command. When executed, the 18-bit code word Y is decoded to:

• Reset the program counter using bits 5-17.
• Load bits 0-2 into the DFW (Data Field Working) register, a 3-bit register that selects one of the eight memory modules for data access.
• Load bits 3-5 into the IF (Instruction Field) register, a 3-bit register that selects one of the eight memory modules for instruction fetches.

The standard 12-bit Memory Address (MA) register selects a specific word within a 4096-word module. In the Type 14 system, the DFW and IF registers work with the MA to determine which of the eight modules is accessed:

• For single-cycle instructions, MA and IF select the memory module and cell.
• For two-cycle instructions, IF specifies the module for the initial address Y, while DFW and MA select modules for subsequent data accesses.
• High-speed channel transfers and break cycles also use the DFW register to specify the memory module.

A related command, sdf Y (set data field), is available to change only the DFW register, thereby switching the data field independently of the instruction field.

The document also details necessary hardware modifications to the PDP-1, including changes to the program counter, accumulator, memory buffer, sense amplifiers, and decoders, to support this field switching. It introduces the DFT (Data Field Temporary) register, which is used to temporarily store the states of DFW and IF during operations like jds (jump and save), cal (call), and sequence breaks, ensuring proper memory context management.