MAINDEC-1 InstrTest

This document describes "MAINDEC 1: Instruction Test," a suite of sixteen programs (numbered octally 1-20) designed to thoroughly test the operations of most PDP-1 computer instructions, excluding the IOT (Input/Output Transfer) group and partially testing the lat instruction.

Key aspects of the Instruction Test include:

1. Purpose: To verify the correct functioning of arithmetic, logical, data handling, shift/rotate, skip, and general operate instructions. It specifically checks deferrable instructions with indirect addressing and augmented instructions with the defer bit set to both 1 and 0.
2. Program 1: This initial program clears memory and loads a RIM (Read-In Mode) loader into high core locations (7772-7777). It does not test any instructions directly but sets up the environment for subsequent tests.
3. Programs 2-20: These programs systematically test individual instructions or groups of instructions. A core principle is that an instruction is generally tested before it is used within its own test program.
4. Operation & Control:
   • The RIM loader automatically loads subsequent programs, but manual read-in is an alternative if the loader fails.
   • Sense Switches (SS1 and SS2) on the console provide control over execution, allowing programs to halt after read-in, execute once, or iterate continuously.
   • The document includes detailed error halts (cause and location) and restart procedures for each program to aid in diagnosing malfunctions.
5. Applications: It outlines procedures for various testing scenarios: a "Full Test" for comprehensive verification, a "Daily Test" for routine checks, handling "Computer Malfunctions," and performing "Margin Checks."
6. Completion: The entire Instruction Test is considered successfully completed when the computer halts with specific contents in its Program Counter (PC), Memory Address (MA), Memory Buffer (MB), Accumulator (AC), In-Out (IO) registers, and all program flags set.

In essence, the document serves as a comprehensive guide for diagnosing hardware issues in a PDP-1 by detailing a structured, multi-program instruction test, its operational procedures, and expected outcomes.