40

This document, "PDP-X Technical Memorandum #40," by L. Seligman, dated January 31, 1968, describes the PDP-X memory bus.

Core Function: The PDP-X memory bus serves as the high-speed interconnection facility between one or more processor modules (or extremely fast I/O devices) and memory modules. Its signals are interlocked to maintain performance over arbitrary distances, and its electrical properties are identical to the I/O bus.

System Organization:

• Components: The primary modules connected to the bus are the processor, memory, and an arbiter.
• Ports: Each processor has a single-ended port, while each memory module has two double-ended ports.
• Arbiter: An arbiter is required for systems with three or more processors, or when two or more Direct Memory Access (DMA) devices are connected to the second memory port (which functions as a DMA channel). The arbiter multiplexes memory access, acting as a DMA multiplexer in some configurations, and must be the last connection to the memory bus.
• Addressing: Memory addressing can be configured; systems without a "protection feature" allow processors to see memory mapped differently, while systems with protection ensure a consistent physical address across all processors.
• Special I/O: Fast I/O devices can substitute for processors on the memory bus, achieving data transfer rates of up to 300,000 words/second practically, with over 1,000,000 words/second possible.

Operation:

• Memory Access: Memory requests are first examined by local memory. If no local memory responds, the arbiter forwards the request to the common memory system.
• Read, Write, Pause Cycles: Detailed signal handshakes (REQ, ADDR ACK, RD RST, MRLS, MRLS ACK) govern memory operations. For instance, a processor sends an address and control, memory acknowledges, and then either sends data (Read), receives data (Write), or pauses before receiving data (Pause).
• Parity: A parity control unit, in conjunction with parity-enabled memory modules, performs parity checking for data transferring between processors and memory. This process introduces a slight delay in the memory cycle.
• Hold and Priority: While memory typically alternates service between requesting ports, a "HOLD" signal allows a high-priority port to maintain exclusive access for high data rate transfers (e.g., over 300,000 words/second), block transfers, or temporarily lock out other processors from a memory area.

The design rationale emphasizes scalability, compatibility with existing PDP-9 systems, and the simplicity of the arbiter, with complex timing and address detection handled by the memory modules. The document also includes figures illustrating system configurations and timing diagrams for memory operations.