33

This document, PDP-X Technical Memorandum #33, dated November 6, 1967, details additions and modifications to the existing PDP-X Instruction Simulator (originally described in Technical Memorandum #18).

Key updates and features include:

• Conformance: The simulator has been updated to align with the PDP-X description found in Technical Memorandum #29.
• IOD Instruction Simulation: All Input/Output Device (IOD) instructions are now simulated, with the exceptions of "Read Console Switches" (RCS) and instructions related to the protection option.
• Multiplexor Channel: The Multiplexor Channel remains unsimulated.

• Enhanced Debugging with Line Printer (Type 647):

  • When the processor stops (due to Disable Memory, Address Stop, Single Instruction, or HLT) and the LPT Enable switch (ACS 12) is active, debugging information (PC, RG, CC, and accumulator group) will be printed.
  • This feature enables single-step tracing and selective tracing (using Address Stop).
  • The processor can automatically continue after stops caused by Address Stop or Single Instruction if the "Repeat" switch (ACS 15) is on.

• EOP Instruction Disabling: For debugging Model I software, EOP (End Of Program) class instructions can be disabled by setting ACS 11, causing them to trap.

• Memory Utilization: The simulator now takes advantage of the full core memory available on a PDP-9, while using 8k when run on a PDP-7.

The document also outlines the functions of various Auxiliary Control Switches (ACS) and provides instructions for loading and restarting the simulator (e.g., restarting at location 22 for an IO Reset, or location 23 to print registers without resetting the PDP-X, useful for breaking loops).