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This technical memorandum outlines the preliminary design for the Control Memory Format of the PDP-X Model II processor.

The PDP-X Model II processor is designed to be controlled by a read-only memory (ROM), implementing a microprogrammed approach. A primary goal of the PDP-X architecture is to achieve commonality across different types of processors (e.g., arithmetic, I/O) for ease of manufacturing, checkout, and service. This is largely accomplished by making the core processor components general, with the primary difference between processor types residing in the ROM-based Main Control unit.

Each 72-bit ROM word functions as a micro-instruction, defining the CPU's state, activating specific control lines, and determining the address of the next micro-instruction. The ROM word is divided into 34 distinct control fields, each governing particular processor functions.

Key features of the ROM control system include:

• Explicit Branching: Micro-instructions explicitly specify their potential successors rather than executing sequentially. This powerful branching capability, based on Branch Field and Branch Condition fields, significantly reduces the total number of ROM words required.
• Microprogram Traps: Exceptional conditions (e.g., errors) can override normal sequencing, forcing a jump to a special, wired-in ROM address, analogous to program traps.
• Technical and Economic Advantages: ROM control offers benefits such as lower component counts, higher reliability, and the flexibility to modify or create instructions by altering the microprogram.

The document proceeds to detail each of the 34 control fields within the 72-bit ROM word, describing their functions related to:

• General control (e.g., constants, branching, traps, interrupts)
• Memory control (e.g., read, write, pause, wait states)
• Result Bus operations (loading various registers)
• Data control (e.g., carry insert, shifts, selections for arithmetic operations)
• A Bus and B Bus inputs (connecting data sources like memory, registers, or constants)
• I/O operations (executing I/O commands, loading I/O registers)
• Miscellaneous control functions (e.g., flag operations, step counter decrement, condition code setting, priority interrupt management).

Appendices provide further explanations of how Fast Memory Addresses are generated and the detailed mechanics of Control Memory Addressing and Branching.