29 Nov67

This document is a revised description of the PDP-X Processor, superseding an earlier technical memorandum (TM #13). It highlights significant architectural changes, emphasizing that the entire document should be read due to the extent of these modifications.

Key areas of major change include:

1. Floating-Point Registers: Their elimination from the memory address space.
2. Program Status Word (PSW): Addition of several new trap conditions and a general rearrangement of the PSW structure.
3. DIV and LDIV Instructions: An additional mode was added to these instructions, enabling integer operations.
4. I/O Instructions: The IOX instruction was eliminated, and IORC (I/O Read Character) and IOWC (I/O Write Character) instructions were added.
5. IOD Class Instructions: Several new IOD instructions were introduced, including HALT and CONSOLE SWITCH operations.
6. Memory Protection: Changes were made to the memory protection instructions.
7. Multiplexor Channel Priority: An additional multiplexor channel priority level (level 8) was added.
8. Device Interrupt Granting: Modifications to how a device is granted an interrupt, including a change in the Status Registers from a LOW bit to a HIGH bit for interrupt priority.
9. Interrupt Handling Memory: A reduction in the number of memory words reserved for handling device interrupts, from 400 (octal) to 200 (octal) words.

Overall System Description:

The PDP-X is a modern, high-performance, third-generation, binary, two's complement computer family designed for the small computer market, offering limited upward and downward program compatibility. It supports standard I/O and Memory interfaces and is designed for fourth-generation hardware and multiprocessor systems. Two members are mentioned: PDP-X/I (PDP-8 class) and PDP-X/II (PDP-9 class).

Processor Architecture:

• Models: PDP-X comes in Model I (basic instructions, core-resident general registers, two priority levels) and Model II (extended instructions, hardware general registers, more priority levels, and options like a Priority Interrupt System and a Protection Option).
• Instruction Formats: It supports various instruction formats (short, basic, long, extended, I/O) with fields for operation code, registers, addresses, and addressing modes.
• Data Formats: Handles fixed-point arithmetic (16-bit words, 32-bit products/dividends), logical data, floating-point data (32-bit short, 64-bit long, using dedicated registers), and 8-bit characters (USASCII).
• Addressing: Uses a 15-bit effective address, supporting direct, relative, immediate, indexed, and linked modes. Specific addresses (0 and 1) have restricted access.
• General Registers: 16 general registers per priority level, with registers 0 and 1 comprising the 32-bit Program Status Word (PSW). Model II can utilize fast, hardware-based registers.
• Program Status Word (PSW): Contains bits for arithmetic traps, error traps (for push-down lists, non-existent memory, address exceptions, I/O errors, privileged instructions, read-only violations), priority of the active process (Register Group - RG), and condition codes (carry, negative, nonzero).
• Instructions: Divided into Basic (available on all models) and Extended (Model II only, traps on Model I). They cover arithmetic, logical, data transfer, control flow, stack operations (Push-Down Group), and extensive I/O operations (IOR, IOW, IOS, IOC, IOD, etc.).

Interrupt System (Priority System):

• Supports up to nine priority levels (main program, various devices, multiplexor channel).
• Interrupts automatically trigger a fast context switch by replacing the current general register set with an appropriate new one, allowing for nested interrupts.
• The Protection Feature (optional for Model IIc) enables multi-user operation with distinct user and monitor modes, instruction protection (user mode cannot execute I/O), memory protection via paging (1K pages, read-only control), and monitor calls for user-monitor communication.

I/O System:

• Architecture: The I/O system is byte and full-word oriented, comprising an I/O section in the CPU, I/O bus, controllers, and devices.
• Data Transfer Modes: Program-controlled (most flexible, slowest), Multiplexor channel (concurrent I/O for multiple devices, time-shared), and Selector channel (high-speed, dedicated to one device for large transfers like disks/tapes).
• Interrupt Handling: Devices signal attention by requesting service at a specific priority level, and the system dynamically manages interrupts based on current process priority and the device's HIGH/LOW status bit.
• Reserved Memory: Specific memory locations are reserved for I/O service routine entry pointers and multiplexor/selector channel command pointers.

The document concludes with assembly language conventions, an alphabetical list of instructions, and detailed flowcharts for I/O operations.