Marketing Suggestions for First Implementations

This document, PDP-X Technical Memorandum #27, outlines marketing conclusions and implementation plans for the PDP-X computer line, based on previous technical memoranda. The core recommendations are:

1. First Products: The initial PDP-X models to be announced and delivered should be fast-memory (0.75 µsec) versions of Level II hardware, featuring an extended instruction set. Configurations would range from a basic 4K model with ASR-33 and a modified Level II assembler/Level I FORTRAN, up to 32K models with high-speed I/O, bulk storage, and API. A background/foreground version of Model II may be announced concurrently or shortly after.
2. Memory Speeds: Two primary memory speeds are proposed: 0.75 µsec (fast) and 2.0 µsec (slow). While all Level II processors should be fast, they should be capable of using slower memories. Level I processors would only be offered with slow memory.
3. Implementation Order:
   • First (simultaneous announcement): Three fast-memory versions of Model II (II1, II2, II3,f).
   • Second: Background/foreground version of Model II (II4,f).
   • Third: Slow version of Model I (Is).
   • Fourth: All slow versions of Model II.
   • Fifth: Any Model III versions. A fast version of Model I is not considered necessary or profitable.
4. Initial Deliveries & Options Schedule:
   • At Announcement (demonstration): A PDP-X with 8-16K, high-speed paper tape, API, and bulk storage; and a 4K PDP-X with ASR-33.
   • First Deliveries (3-4 months after announcement): High-speed paper tape I/O, extra memory (up to 32K), and DECtape.
   • Within 4-6 Months: All CPU options, small displays, A/D and D/A equipment, IBM-compatible magnetic tape, disc drives, card readers, and line printers.
   • Within 8-12 Months: Memory protection, large displays, and 360 interfaces.
5. Further Plans (12-18 months after initial intro): Subsequent announcements would include background/foreground Level II models (if not initial) and Model I processors. Slower-memory Model II processors could follow if significant cost savings are realized.

The document emphasizes establishing the PDP-X architecture as "best in the field" with state-of-the-art hardware and memory speeds, while acknowledging the potential for cost savings with slower memory options later.