26 Oct67

This document, PDP-X Technical Memorandum #26 (dated October 5, 1967), details the event sequences on the PDP-X Input/Output (IO) Bus. Authored by H. Burkhardt, it focuses on the additional features and the interlocked operations of the bus, explicitly excluding electrical and mechanical characteristics.

The IO Bus connects IO device control units to the central processor and offers facilities such as multiplexor channel I/O, data packing, priority interrupt synchronization, and the ability to specify arbitrary memory locations for data transfers. It consists of 8 bi-directional data lines and 32 control lines, further divided into:

• 8 outbound control lines (Command Out, from processor to device)
• 8 inbound control lines (Response In, from device to processor)
• 8 inbound priority request lines (one per priority level, from devices to processor)
• 8 outbound priority grant lines (one per priority level, from processor to devices)

The document categorizes bus activities into two main types:

1. Processor-Initiated Activity: This is driven by processor I/O instructions (e.g., IOR, IOW for data, IOS, IOC for status, RIO for reset). The sequence typically involves the processor sending a Device Address and SYNC signal, a device responding with RTN, followed by specific data or status transfer sequences (e.g., one-byte or two-byte input/output).

2. Device-Initiated Activity: This occurs when a device requests service (e.g., task completion, unusual condition) by raising its assigned priority request line. Upon the processor granting the request, the device places its address and a HIGH bit on the data lines. The processor then determines if a channel operation is required, leading to further sequences that can involve:

   • Updating Byte Counters (BC) and Byte Addresses (BA) in various modes.
   • Different data transfer types: Output (OUT), Input (IN), or Add-In (reads, adds, stores, and transmits the sum).
   • Mechanisms for handling channel overflow and add overflow during multi-byte operations.

The appendix provides detailed flowcharts illustrating these bus sequences for various operations, including single and two-byte input/output, interrupt handling (with or without channel operations), and specific channel functions like reading 16-bit addresses, counting-only operations, and single-byte input/output/add-in.