PDP-X/II Register Section (Proposed)

This document describes a proposed register organization for the PDP-X/II processor, focusing on its functional components and timing. Designed around a 200-nanosecond internal cycle, the system can perform a 16-bit addition (e.g., between a fast memory word and the AR register) with rewrite into fast memory, accommodating 15 nanoseconds for control memory skew. A notable feature is the ability to concurrently shift the MI register during main operations, facilitating multiply and divide steps.

The register section is composed of five interdependent parts:

1. Registers (AR, MI) and Fast Memory (FM): These hold temporary data essential for instruction fetching, address calculation, and execution. The Arithmetic Register (AR) stores partial computational results, while the Memory Interface (MI) register handles addresses and data destined for the memory system. Fast Memory (FM) stores critical state information such as accumulators, index registers, and the program counter.
2. Input Gates and Latch: These control the flow of data to the adder's A and B buses. The B bus typically receives memory instruction words or data operands (in true or complemented form), while the A bus usually receives accumulator or index register operands from FM. A latch mechanism disconnects input signals during bus operations but retains data for the adder, which is crucial given that FM cannot simultaneously read and write.
3. Conditional Sum Adder: This is a high-speed, 16-bit adder structured into four 4-bit groups. It calculates conditional sums in parallel based on assumed carry-ins and then selects the correct sum, significantly speeding up addition.
4. Selector: This component serves multiple purposes: it gates the appropriate conditional sum from the adder, performs logical AND operations, and enables shifting of the MI register. During MI shifts (e.g., for divide operations), it bypasses the adder, allowing the adder to concurrently perform other calculations.
5. Shifter: This unit offers versatile data manipulation for output, allowing data to be entered into registers, memory, or fast memory as-is, shifted one bit right or left, or with its bytes interchanged.

The document also details timing assumptions, including gate delays and setup times for various components, and describes the data flow within a 185-nanosecond register cycle. The overall 200-nanosecond processor internal cycle is governed by a recirculating delay line timing generator. Control signals and specific control memory word bits are defined, emphasizing the need for precise signal availability and interlocks to ensure proper sequencing and maximum operating speed.