Processor/Memory Timing Relations

This technical memorandum, PDP-X Technical Memorandum #21, examines the timing relationships between the central processor hardware (registers, gates, adders) and the main memory system for the PDP-X. The analysis aims to establish speed requirements for both the central processor and the control memory.

Key assumptions include a main memory cycle of less than 1 microsecond, processor time states initiated by memory signals (ADDR ACK and RD RST), continuous full-speed memory operation, a 50 NS cable delay, and three processor cycles per main memory cycle. Based on these assumptions, the document derives several timing constraints, expressed as inequalities, relating Main memory cycle time (M), control memory Access time (A), and processor Cycle time (C).

For the fastest achievable memory system (M = 750 NS), applying a 20% safety factor, the analysis suggests a control memory access time of 100 NS and a central processor cycle time of 180 NS. However, the authors conclude that these speeds are difficult to achieve based on preliminary design and experience with previous systems (like the PDP-9). Therefore, a slower, more cost-effective memory system is proposed, leading to revised guidelines: an 800 NS main memory (read-restore) cycle, a 200 NS processor internal cycle, and a 120 NS control memory access time. The document includes several figures illustrating timing diagrams and the derived constraints.