Preliminary Memory Bus Description

This document describes the PDP-X memory bus, an interconnection facility designed for communication between one or more processor/fast I/O modules and memory modules. Its electrical properties are identical to the I/O bus, and its interlocked signals allow for long connection lines without performance degradation when memory is close.

The system is organized around three types of modules: processors, memory modules, and an arbiter. Processors have a single port, while memory modules have two double-ended ports, one of which can be connected to an arbiter for priority access. An arbiter is required when there are two or more local memory systems, multiplexing the second memory port to make it available to all processors. While processors can simultaneously access their local memory, only one processor can access the entire memory system via the arbiter at any given time. The arbiter, typically the last connection to the memory bus, handles requests for non-local memory.

The bus utilizes 20 bidirectional address/data lines (I0-24) and two control signals (C0,1) for operations like read/restore and clear/write. Key handshake signals include RQ (memory request), ADD RACK (address acknowledge), RD RST (read restart), WR RST (write restart), and ADDR EXIST (address recognition).

Parity is implemented for local memory systems by adding a parity control unit and dedicated parity memory (4k x 16-bits). Parity calculations run in parallel, 1/3 cycle behind main memory, ensuring no impact on the memory cycle rate. The system can optionally halt upon detecting a parity error. Special high-speed I/O devices can also connect to the memory bus, mimicking processor interfaces while having an additional I/O bus for control.