PDP-X Processor Description

This document provides a comprehensive description of the PDP-X computer family's architecture, instruction set, and I/O system. Designed as a modern, high-performance, third-generation binary, two's complement system for the small computer market, PDP-X emphasizes program compatibility and supports multiprocessor systems.

The family comprises two primary models: the basic PDP-X/I, featuring core-resident general registers and a fundamental instruction set, and the advanced PDP-X/II, which incorporates hardware general registers and an extended instruction set. The PDP-X/II can be optionally enhanced with a Priority Interrupt System and a Memory Protection feature, along with expanded memory capacity.

The processor architecture details flexible instruction formats (short, long, extended operation, and I/O) and a variety of data types, including fixed-point (single and double precision), floating-point (short and long), and character operations with byte-level addressing. It supports multiple addressing modes (direct, relative, immediate, indexed, linked). The system includes 16 general registers per priority level, with the Program Status Word (PSW) managing processor state, trap conditions, and condition codes. Dedicated floating-point registers are available at lower priority levels.

The instruction set is categorized into basic operations (load, store, arithmetic, branch, modify), extended arithmetic, character manipulation, logical compare and modify, and a push-down (stack) group. A dedicated I/O instruction class includes commands for managing the Priority System and Memory Protection. The Priority Interrupt System handles up to eight nested priority levels, automatically switching register sets during interrupts. Memory protection is achieved via a paging system that supports user and monitor modes, using mapping registers to control memory access and facilitate re-entrant code execution. Traps are triggered for protection violations.

The I/O system is byte and full-word oriented, offering three data transfer modes: program-controlled (for flexibility), a multiplexor channel (for concurrent, time-shared I/O), and a high-speed selector channel (for dedicated device transfers). Peripherals conform to a standard status register structure with common control bits. The document includes examples of paper tape and keyboard/printer peripherals, along with detailed descriptions of the I/O bus and its timing. Appendices outline assembly language conventions and an alphabetical listing of all instructions.