Detailed Model Specifications

This document outlines the proposed PDP-X computer models, detailing their expandability and compatibility. It describes a range of system performance available across the different models, which are generally categorized into Model I and Model II.

The smallest model, Model I, features no hardware general registers, uses two priority levels (main program and interrupt), and stores program counter and accumulators in memory, making it slower than Model II. It includes a basic instruction set, supports memory expansion from 4K to 32K, and operates asynchronously with memory for cost efficiency (e.g., 8 micro-second memory, resulting in a 32 micro-second add time for Model Ia, or 3 micro-second for Model Ib). While its basic register subassembly is shared with larger models, a Model I processor cannot be upgraded to a Model II processor, though other system components can be reused.

The medium-sized Model II comes with two sets of hardware general registers, two priority levels, and an instruction set that includes both basic and extended instructions. Its standard configuration includes High-Speed Paper Tape, a 33 KSR Teletype, and 8K memory. With program counter and accumulators in fast memory, it achieves a faster 2 memory cycle add time (1.5 micro-seconds for Model IIa, IIb, IIc). Model II processors are highly expandable, with options to add a Priority Interrupt System (including additional general registers and interrupt handling), a Protection Option (enabling user/executive modes, memory paging, and related instructions, which requires the Priority Interrupt System), Power Fail, Memory Parity, Machine Check hardware, and memory expansion up to 32K or 128K (with the Protection Option).

A table further details specific sub-models (Ia, Ib, IIa, IIb, IIc), differentiating them by register sets, instruction sets, standard memory, I/O, interrupt structure, protection systems, and performance metrics like add, multiply, and index times.