4381542 System For Interrupt Arbitration Oct80

This patent describes a system for interrupt arbitration in a data processing system with a common bus connecting a processor, memory, and multiple I/O units, all with pre-assigned priorities.

The key innovation is that after a unit requests and is granted an interrupt by the processor, it does not immediately transfer the interrupt information (vector). Instead, the interrupting unit must then compete in a bus arbitration process with other units to gain control of the system bus. This allows higher-priority data transfers, such as memory information, to occur on the bus before the interrupt vector is transmitted.

Only after the interrupting unit successfully arbitrates for and gains control of the bus (meaning no higher-priority unit needs to make a transfer) does it then transmit the interrupt vector to the processor. This mechanism ensures that critical, high-priority data transfers are not delayed by the transmission of interrupt information, even if the interrupt has already been acknowledged by the processor.