W706

This document is a proprietary schematic diagram for a Digital Equipment Corporation (DEC) Teletype Receiver, model W706, copyrighted 1966. It is intended for test and maintenance purposes.

The circuit's primary function is to receive serial teletype data and convert it into parallel output signals, while also generating various control and status indicators.

Key functional blocks and features include:

• Inputs: A "TELETYPE SERIAL INPUT AF" for the serial data stream and a "CLOCK INPUT BS" for synchronization.
• Data Conversion & Storage: The serial input is processed and stored in a series of flip-flops (E7, E9, E11, E13, E15) labeled "BIT 1 CODE" through "BIT 8 CODE", effectively converting the serial data into a parallel 8-bit word.
• Outputs: The parallel data bits are presented at "BIT 1 OUTPUT" through "BIT 8 OUTPUT" via output transistors (Q3-Q10). Additional status and control outputs include "READER RUN", "FLAG OUTPUT", "STROBED FLAG OUTPUT", "READ STROBE", and "ENABLE".

• Timing and Control Logic: Extensive logic circuitry, including various gates (NAND, NOR, AND, OR) and flip-flops, manages the communication protocol. This includes:

  • Detecting and managing "STOP TIME" units (1.0, 1.5, 2.0 units) crucial for serial communication.
  • Generating "POWER CLEAR" and "CLEAR FLAG" signals.
  • Controlling the "READER RUN" state.
  • A "FREQ DIVIDE" circuit (E3) for clock management.

• Components: The schematic details specific transistor types (DEC6534B, IN3606), diodes (D664), and integrated circuits (MC899P, MC824P, MC890P), along with standard resistors and capacitors.