S111

This document is a schematic diagram for a "DIODE GATE SIII" circuit, designed by Digital Equipment Corporation in 1965.

Key information includes:

• Purpose: The schematic is provided for test and maintenance purposes, and the circuits are proprietary.
• Circuit Design: It depicts a multi-input diode-transistor logic (DTL) gate with three main stages (Q1, Q2, Q3), each featuring a transistor, associated input diodes, and pull-up resistors.

• Components:

  • Transistors: DEC 3639 (EIA equivalent: 2N3639).
  • Diodes: Primarily D-662 (EIA equivalent: 1N645) and D-664 (EIA equivalent: 1N3606).
  • Resistors: Generally 1/4 Watt with 10% tolerance, unless otherwise indicated (specific resistance values like 100,000Ω, 15,000Ω, 3,000Ω, 1,500Ω are shown).
  • Capacitor: One 0.01 MFD capacitor (C1).

• Power Supplies: The circuit operates with +10V(A), Ground (GND), and -15V lines. A -3V "STRATE" point is also indicated.

• Drawing Details: The document is Revision D, drawn by I. Hahn on June 10, 1965, and checked/engineered by R. Silverman and R. Sogge on June 18, 1965. It specifies that the printed circuit revision for the DGL board is SIA.