M765

This document is a schematic diagram for a "READ BUFFER" circuit, identified as M765-0-1, created by Digital Equipment Corporation (DEC) and dated December 3, 1969.

The diagram details a digital logic circuit primarily composed of several integrated circuits, including:

• D-type flip-flops (DEC7474N, e.g., E1, E5, E9).
• 8-bit registers/latches (DM8570, e.g., E2, E4, E6).
• Quad 2-input NAND gates (DEC7400N, E3).
• Hex Open-Collector Inverters/Buffers (DEC7405N, e.g., E11, E14).

The circuit features various input signals such as CLOCK L, CLEAR H, DELAY STROBE L, SHIFT ENABLE H, BUFFER CLEAR L, START SKEW DELAY L, and WINDOW E1. It also includes numerous test points (TPP, TP0-TP7) and output lines (e.g., S0-S7, Q1-Q8 groups). Standard TTL power (+5V) and ground connections are specified for the ICs.

Passive components like resistors (1/4W, 5%) and capacitors (0.1MFD, 100V, 20%) are also shown with their general specifications. The document includes a disclaimer that the schematic is for "test and maintenance purposes only" and is proprietary.