M720

This document is a schematic diagram for the Digital Equipment Corporation (DEC) Memory Detection M720 circuit, part number M720-0-1, Revision A, copyrighted in 1967.

The schematic is provided for test and maintenance purposes and is noted as proprietary to DEC. The circuit is a digital logic design composed of:

• Discrete components: Resistors (1/4W, 5%), capacitors (unless otherwise indicated, 0.01 MFD), D664 diodes (EIA: IN3606), and DEC3009B transistors (EIA: 2N3009).
• Integrated Circuits (ICs): DEC7400N gates (used for E1, E3, E4) and DEC7460N gates (used for E2), with standard pin 7 for GND and pin 14 for +5V.

The circuit appears to take a "MEM START V" input and processes it through a series of logic gates, timing capacitors (e.g., C9, C11, C7, C8, C10), and transistor stages to generate output signals such as "STROBE E" and "MEM DONE D", along with a "RUN (1)" output. It also includes "S" and "T" inputs and "T.P." (Test Point) connections. The design suggests a role in precisely timing and controlling various aspects of memory operations.