M709

This document is a schematic diagram for the Digital Equipment Corporation (DEC) Clock Counter M709, copyrighted in 1988. It is described as proprietary, intended solely for test and maintenance purposes.

The schematic details a 12-bit digital counter circuit that processes parallel input data and provides various control and output signals:

• Inputs: It features 12 parallel "I/O BUS IN" lines (00 through 11) that feed into clock registers (E1-E6) and subsequently into count registers (E13-E18).
• Counting Mechanism: The core of the circuit consists of multiple integrated circuit flip-flops (e.g., DEC7474N) arranged to form the clock and count stages, incrementing based on a "CLOCK TO COUNTER" input.
• Control Functions: Includes dedicated inputs for "LOAD COUNTER," "GATE" (enabling/disabling the counter), "SET COUNTER," and "CLK AC CLR" (Clock AC Clear).
• Outputs: Provides 12 buffered outputs (ACO0-ACO11), an "OVERFLOW" indicator, and two separate read-out points for the count value ("READ 0-5 T.P." and "READ 6-11 T.P.").
• Components: The circuit is constructed using standard TTL integrated circuits (various DEC74XX series, primarily NAND gates and D-type flip-flops), along with resistors, capacitors for power supply decoupling, and a diode.