M163

This document is a schematic diagram, copyrighted in 1969 by Digital Equipment Corporation, for a Dual Binary to Decimal Decoder (Model M163-0-1, Revision A).

The schematic details the circuit for two identical binary-to-decimal decoders, likely utilizing Fairchild 9301 integrated circuits (ICs). Each decoder takes a 4-bit binary input (represented by pins A0-A3, with external labels like BI, CI, DI, EI for the first decoder and D2, E2, F2, H2 for the second) and translates it into 10 distinct decimal outputs (0 through 9).

Key circuit specifications include:

• Power: +5V and Ground (GND).
• IC Connections: Pin 16 of each IC is connected to +5V, and Pin 8 to GND.
• Capacitors: Two .01 MFD capacitors (C1, C2) are used for power decoupling, connected between the +5V supply and ground.

The document explicitly states that it is for test and maintenance purposes only and that the circuits are proprietary. It was drawn by BUTLER on July 29, 1969, and engineered by A. Chandha on October 7, 1969.