G859

This document is a proprietary schematic diagram for a "Clock & Regulator G859" circuit, copyrighted in 1969 by Digital Equipment Corporation and intended for test and maintenance.

The circuit design includes:

• Input Logic: Several inputs (K, S, P, L, J, H, F, E) are processed by DEC7401 logic gates, operating with standard TTL power supply pins (+5V on Pin 14, GND on Pin 7).
• Clock Generation: Two distinct oscillator sections, labeled "OSC. Ø N" and "OSC. 1 M," likely implemented using cross-coupled transistor pairs (Q2/Q3 and Q6/Q7) with associated resistors and capacitors.
• Voltage Regulation: Features a Zener diode (D5, IN752A) and other components for voltage regulation.

The schematic specifies various components, including transistors (DEC6531, DEC6534B, 2N4923), diodes (D664), resistors, and capacitors, with general specifications provided (e.g., 1K, 1/4W, 5% resistors; .39MFD, 100V, 10% capacitors). The circuit operates with +10V, +5V, -15V, and GND power rails. A "Transistor & Diode Conversion Chart" maps Digital Equipment Corporation part numbers to their EIA/JEDEC equivalents. The drawing was drafted by Butler and engineered by E. Luttig in late 1969.