Digital Semiconductor 21172

This Technical Reference Manual, a draft version from April 1996, provides a detailed technical overview and reference for engineers designing uniprocessor systems using the Digital Semiconductor 21164 Alpha microprocessor in conjunction with the Digital Semiconductor 21172 Core Logic Chipset.

The chipset is composed of two main types of chips:

1. 21172-CA (CIA - Control, I/O Interface, and Address Chip): This central chip provides control functions for main memory, acts as a bridge to the 64-bit PCI bus, and manages address paths. It includes functional units for instruction and address logic, memory control (handling RAS/CAS, memory refresh, and timing), I/O address logic with buffering and increment capabilities, and DMA address logic with direct and scatter-gather mapping (featuring an 8-entry Translation Lookaside Buffer or TLB). The CIA also handles ECC generation and checking for data transactions.
2. 21172-BA (DSW - Data Switch Chip): Four DSW chips are required to provide the complete data path. These chips primarily consist of data buffers and multiplexers, facilitating data flow between the 21164 microprocessor, main memory arrays, the L3 backup cache (Bcache), and the CIA (for PCI data). It includes victim buffers, I/O read/write buffers, and DMA buffer sets, all operating with ECC-protected data paths.

Key features and functionalities of the 21172 Chipset include:

• System Integration: Supports high-performance uniprocessor systems with the 21164 Alpha CPU, Bcache (0MB to 64MB, write-back, ECC-protected), and up to 8GB of ECC-protected physical memory.
• PCI Interface: Provides a high-performance 64-bit PCI interface with multiplexed address and data, 64-bit PCI address handling, and scatter-gather map support, minimizing the need for external "glue logic."
• Address Mapping: Details how 21164 physical addresses (40-bit) are mapped to memory and I/O spaces, including dense, sparse, configuration, and byte/word PCI spaces. It describes the use of programmable address windows and translation methods (direct and scatter-gather).
• Data Coherency: Implements a flush-based data coherency protocol to ensure consistency across the 21164 caches, memory, and PCI devices, managing atomic operations and "post and run" I/O write transactions.
• Clocking: Defines system clock generation from the 21164 internal clock, used for PCI timing (up to 33 MHz).
• Control and Status Registers (CSRs): Provides a comprehensive programmer's reference for configuring memory timing, system parameters, address translation, diagnostics, error reporting, and performance monitoring.
• Initialization: Describes the power-up sequence and the initialization of critical registers by SROM code.

The document serves as a technical resource, detailing pin descriptions, architectural overviews, functional units, transaction flows, and register definitions for both the CIA and DSW chips.