G604

This document is a schematic diagram for a Memory Selector Matrix G604 (Drawing Number CS B-G604), designed by Digital Equipment Corporation in early 1965.

The circuit employs a diode-transformer array to facilitate the selection of specific memory locations for either READ (C) or WRITE (B) operations. It features multiple address or selection inputs (e.g., A, D, E, F, H, J) which drive four identical T-2052 transformers (T1-T4) through an arrangement of D-670 diodes (D1-D16). The transformers provide outputs (e.g., M, N, P, R, S, T, U, V) from their secondary windings, intended to interface with memory storage elements.