G102

This document is a detailed schematic for a Digital Sense Inhibit-Card, model G102, designed on April 10, 1969, by Equipment Corporation.

The card features four independent processing channels, each handling two "sense" inputs (e.g., SENSE 1A and SENSE 1B). Each channel's input stage includes a transformer (T1-T4) and an MC1540 Quad Line Receiver (E7-E10) to process these sense signals.

The core of the card's logic processes these inputs along with external control signals such as "DATA #IN", "CLOCK", "RESET", "INH TIME", and "DATA STR" (Data Strobe). This digital processing relies on various TTL integrated circuits: DEC7474 Dual D-Flip-Flops (E1, E6), DEC74H40 Dual 4-input NAND Buffers (E3, E4), and DEC74H01 Quad 2-input NAND Gates (E5), in conjunction with DIP-packaged transformers (E2 components).

Each channel outputs a "DATA OUT" signal and an "INH" (Inhibit) signal, driven by DEC 2007 transistors (Q1-Q4). The card operates using multiple power rails: +5V, -6V, and -15V. The "Inhibit" functionality suggests that the card is designed to selectively enable or disable the sense data output based on its internal logic and control inputs.