G050

This document is a schematic for the "READ AMPLIFIER G050" designed by Digital Equipment Corporation in 1968, intended for test and maintenance purposes.

The circuit primarily features:

1. Input/Power Conditioning Stage (Top Left): This section utilizes discrete transistors (Q1-Q4, type DEC6534B) and associated passive components, operating on +5V and -15V power rails. It appears to handle initial signal buffering or power supply management.
2. Nine Differential Amplifier/Receiver Channels (E1-E9): These are the core of the read amplifier. Each channel uses a DEC1520 Integrated Circuit, which is described as a differential line receiver or comparator. Each channel receives differential input signals via "P/O CONN2" and includes resistor-capacitor networks for input coupling and feedback to configure the amplification and conditioning.
3. Output Stage: The output of each amplifier channel passes through diodes (type D584) and resistors, generating distinct output signals such as ALI, ANI, ARI, BDI, BFI, BJI, BLI, BNI, and BRI.

The main amplifier channels (E1-E9) are powered by +5V and -7V rails. Default component values are specified: resistors are generally 10K (1/4W, 5%), and capacitors 10pf (100V, 5%), unless otherwise indicated.

In summary, the G050 Read Amplifier is a multi-channel, differential signal conditioning circuit from the late 1960s, designed to amplify and process signals, likely from a data storage system such as magnetic core memory, utilizing early integrated circuit technology.