Alpha 21164 Microprocessor Hardware Reference Manual

This document is the Compaq Alpha 21164 Microprocessor Hardware Reference Manual, a comprehensive technical guide for system designers and programmers working with the Alpha 21164 microprocessor. Published in December 1998, it supersedes previous versions.

The manual covers:

1. Introduction to the Alpha Architecture and 21164 Features:

   • Describes the Alpha as a 64-bit load/store RISC architecture emphasizing speed and multiple instruction issue.
   • Highlights the 21164's superscalar, pipelined design (0.35-µm CMOS, 499-pin IPGA), capable of issuing four instructions per cycle.
   • Notes support for various integer (8- to 64-bit) and floating-point data types (IEEE and VAX formats).
   • Explains the role of "PALcode" (Privileged Architecture Library code) in providing operating system primitives like context switching, interrupts, exceptions, and memory management.

2. Internal Architecture:

   • Details the major functional units:
     • Instruction Fetch/Decode Unit (IDU) and Branch Unit: Manages instruction fetching, decoding, issuing (up to four instructions in parallel), branch prediction, instruction/data translation buffers (ITB/DTB), and interrupt handling.
     • Integer Execution Unit (IEU): Contains dual 64-bit integer pipelines with adders, logic, shifters, and an integer multiplier.
     • Floating-Point Execution Unit (FPU): On-chip, pipelined unit supporting IEEE and VAX floating-point operations.
     • Memory Address Translation Unit (MTU): Handles virtual-to-physical address translation (43-bit virtual, 40-bit physical), manages Miss Address File (MAF) for load merging, and includes a write buffer.
     • Cache Control and Bus Interface Unit (CBU): Manages all memory-related external interface functions, including cache coherence protocols.
   • Describes the chip's on-chip cache hierarchy: an 8KB virtual Icache, an 8KB physical Dcache, and a 96KB 3-way set-associative physical Second-Level Cache (Scache). It also supports an optional external third-level cache (Bcache).
   • Outlines pipeline organization, instruction scheduling and issuing rules (including latencies and replay traps), and performance measurement support via on-chip counters.

3. Hardware Interface and External Operations:

   • Provides a detailed list of all 21164 signal names, types, and functions.
   • Explains clock generation, system clocking schemes, physical address regions, and data wrapping.
   • Covers Bcache structure, cache coherency protocols (write-invalidate and flush-based), lock mechanisms, and various 21164-initiated and system-initiated transactions (e.g., READ MISS, WRITE BLOCK, MEMORY BARRIER).
   • Discusses data bus and command/address bus contention, interface restrictions, race conditions, and data integrity (ECC and parity) mechanisms.

4. Internal Processor Registers (IPRs) and PALcode:

   • Catalogs and describes the extensive set of internal processor registers (IPRs) within the IDU, MTU, and CBU, which are used for configuration, control, status, and diagnostics.
   • Details the Privileged Architecture Library Code (PALcode) environment, its invocation mechanisms (e.g., reset, exceptions, interrupts, CALL_PAL instructions), and specific implementations of architecturally reserved opcodes.

5. Initialization, Error Handling, and Physical Specifications:

   • Explains the chip's initialization and configuration sequences, including power-up reset, clock setup, built-in self-test (BiSt), and serial ROM loading for the instruction cache.
   • Describes the error detection and handling strategy, including parity errors in caches, ECC errors, fill timeouts, and machine check flows.
   • Provides electrical characteristics (voltage, current, timing for various signals), thermal management considerations (operating temperature, heat sinks), and mechanical data (package dimensions, pin assignments).

In essence, this manual serves as a complete technical blueprint for integrating, configuring, and programming systems based on the Compaq Alpha 21164 microprocessor.