M8105

This document is an Engineering Change Order Log issued by Digital Equipment Corporation, detailing modifications for the M8105 (KB11-A Timing and Miscellaneous Control) board used in the PDP-11/45 processor.

Spanning from March 1972 to November 1973, the log outlines various hardware and firmware problems identified with the M8105 board and their corresponding corrections. Issues addressed include:

• Manufacturing etch errors.
• Priority arbitration malfunctions.
• Processor hanging conditions and incorrect address calculation.
• Parity errors (requiring a new M8110 design for full implementation, often in conjunction with other FCOs).
• MOS memory data corruption during abort traps.
• Incorrect data placement on the UNIBUS due to internal register references.

For each reported issue, the document provides a detailed correction procedure (often involving physical rework like cutting etches, adding jumpers, or replacing integrated circuits), notes on diagnostic testing, specific in-plant and field effectivity instructions, estimated installation times, and required kit contents. Some entries highlight dependencies on other related Field Change Orders (FCOs) for complete resolution. The overall purpose is to track and implement necessary fixes to ensure the stability and correct operation of the PDP-11/45 system.