This document is a Data Sheet for Digital Equipment Corporation's Alpha 21066 and Alpha 21066A microprocessors, superseding a previous version.
It provides comprehensive technical specifications and details for system designers and developers, covering:
- Microarchitecture: An in-depth overview of the chips' internal organization, including the core CPU (Instruction Fetch/Decode, Integer Execution, Load/Store, Floating-Point, and Branch Units), on-chip 8KB instruction and data caches, memory controller, and I/O controller (PCI Local Bus Specification, Revision 2.0 compliant). It describes pipeline organization (7-stage for integer/memory, 10-stage for floating-point) and various internal components like translation buffers, interrupt handling, and performance monitoring.
- 21066A Enhancements: Highlights improvements in the 21066A model, such as an improved branch prediction scheme, revised write buffer unload logic, and longword cache parity.
- Pinout: Detailed lists and descriptions of all external signals and their associated pins.
- Electrical Specifications: Absolute maximum ratings, supply current, power dissipation, chip power supply sequencing, and detailed DC and AC operating parameters.
- Mechanical Specifications: Diagrams and dimensions of the 287-pin standard pin grid array (PGA) package.
- Thermal Specifications: Operating temperature ranges and thermal resistance information, including heat sink recommendations.
- Register and Instruction Summaries: Overviews of implementation-specific internal processor registers, memory controller registers, I/O controller registers, and a summary of the Alpha architecture instruction set, including PALcode and VAX compatibility instructions.