Alpha 21164 Microprocessor Hardware Reference Manual

This document is the Alpha 21164 Microprocessor Hardware Reference Manual, published by Digital Equipment Corporation in July 1996. It serves as a comprehensive technical guide for system designers and programmers using the Alpha 21164 microprocessor.

The manual covers:

1. Introduction to the Alpha Architecture and 21164 Features: It introduces the Alpha as a 64-bit load/store RISC architecture emphasizing speed and multiple instruction issue. The 21164 is highlighted as a superscalar, pipelined processor (0.5-micron CMOS, 499-pin IPGA) capable of issuing four instructions per cycle. Key on-chip features include an 8KB instruction cache (Icache), an 8KB data cache (Dcache), a 96KB second-level cache (Scache), a memory management unit (MMU) with Translation Buffers (ITB, DTB), two high-throughput floating-point units, and a six-entry write buffer. It also supports an optional external third-level cache (Bcache) and features a 128-bit data bus with ECC/parity.
2. Internal Architecture: This section details the functional units (Ibox, Ebox, Fbox, Mbox, Cbox), pipeline organization (7-stage integer, 9-stage floating-point), and instruction scheduling rules (slotting, latencies, issue rules). It explains mechanisms like replay traps, the Miss Address File (MAF) for load merging, store instruction execution, and the write buffer with its associated Write Memory Barrier (WMB) instruction for ensuring write ordering. Performance measurement support via on-chip counters and the Floating-Point Control Register (FPCR) are also described.
3. Hardware Interface and External Functionality: The document lists and defines all external hardware interface signals, describing their functions and logic symbols. It elaborates on clocking schemes (CPU, system, and reference clocks for multiprocessor synchronization), physical address considerations (memory regions, data wrapping), and the structure and operation of the optional Bcache. It provides extensive detail on cache coherency protocols (write invalidate and flush-based), lock mechanisms, and various 21164-initiated and system-initiated bus transactions, including timing diagrams and interface restrictions. Potential race conditions and data integrity features like ECC and parity are also addressed.
4. Internal Processor Registers (IPRs) and PALcode: It provides a detailed listing and description of the 21164's internal processor registers, which control and provide status for various functional units. It also describes the Privileged Architecture Library (PALcode), a set of operating-system-specific macrocode routines crucial for handling context switching, interrupts, exceptions, and memory management, including special PALmode-only instructions.
5. Initialization, Configuration, Error Handling, and Physical Data: The manual covers the processor's reset sequence, sysclk ratio and delay configuration, built-in self-test (BiSt), and cache initialization procedures. It details comprehensive error detection and handling strategies, including machine checks and correctable error interrupts. Finally, it provides electrical data (characteristics, power supply considerations, clocking scheme timings), thermal management guidelines, and mechanical packaging information.

In essence, this manual serves as the definitive hardware specification for the Alpha 21164, guiding engineers in designing, integrating, and programming systems based on this microprocessor.