DQS11-C

This document is an Engineering Change Order Log from Digital Equipment Corporation for the DQS11-C DMA Controller, used with the PDP-11 Family of processors. It details three significant engineering changes (FCOs) implemented in 1973 to address various functional issues:

1. DQS11C-B0001 (Mar-73): Corrected a problem where the BCC (Block Check Character) was not transferred to memory if it matched the SYNC code. The fix involved modifying logic and replacing specific components to enable proper input data transfer. This was an immediate retrofit for all DQS11-C units.
2. DQS11C-C0002 (May-73): Enabled parity logic for SYNC and EOT (End of Transmission) characters, and added CLEAR TO SEND and REQUEST TO SEND control logic to improve half-duplex operation. This also required an immediate retrofit for all units.
3. DQS11C-E0003 (Nov-73): Introduced a product improvement allowing the DQS11-C to be initialized by a new instruction, in addition to SYSTEM INITIALIZE or reset. This added CLEAR AND GO (via Receive Status Word bit zero) and RESUME (via Receive Status Word bit seven) functions for enhanced control. This change was implemented in new production units and retrofitted for existing DQS11-C's only upon customer request.

All changes involved specific hardware/logic modifications, with field retrofits requiring between 1.0 to 2.5 hours for installation and testing, along with documentation costs and labor charges at the then-current hourly rate.