Alpha 21164 Microprocessor Data Sheet

This document is the Alpha 21164 Microprocessor Data Sheet, providing a comprehensive technical overview of the processor.

Key aspects summarized include:

• Core Features: Describes the Alpha 21164 as a fully pipelined, 64-bit advanced RISC architecture supporting multiple operating systems (Windows NT, OSF/1, OpenVMS). It operates between 266 MHz and 300 MHz, features superscalar 4-way instruction issue, and boasts a peak execution rate of 1200 MIPS, built on 0.50-µm CMOS technology.
• On-Chip Caches: It details three integrated caches: an 8KB direct-mapped L1 instruction cache, an 8KB dual-ported, direct-mapped, write-through L1 data cache, and a 96KB 3-way set-associative, write-back L2 data and instruction cache. It also supports an optional board-level L3 cache ranging from 1MB to 64MB.

• Microarchitecture: Outlines the major functional units:

  • Instruction Fetch/Decode and Branch Unit (Ibox): Manages instruction fetching, decoding, branching, and on-chip instruction translation buffers (ITBs), including interrupt and exception logic.
  • Integer Execution Unit (Ebox): Contains two 64-bit integer pipelines with multiple arithmetic and logic units, a barrel shifter, and an integer multiplier.
  • Floating-Point Execution Unit (Fbox): A pipelined unit supporting IEEE (S/T) and VAX (F/G, limited D) floating-point data types, with specific details on exception handling (Invalid, Divide-by-zero, Overflow, Underflow, Inexact, Integer Overflow).
  • Memory Address Translation Unit (Mbox): Handles data translation (DTB), manages a Miss Address File (MAF) for load merging, and includes a write buffer.
  • Cache Control and Bus Interface Unit (Cbox): Manages on-chip caches (L2) and the optional external L3 (Bcache), implements coherence protocols, and controls the 128-bit bidirectional data and address buses.

• Pipeline Organization: Describes the 7-stage pipeline for integer operations and memory references, and a 9-stage pipeline for floating-point operations.

• Interfaces: Details the 499-pin interstitial pin grid array (IPGA) package, including pin assignments and signal descriptions for system commands, data transfer, clocks, interrupts, and test modes (Serial ROM Interface, JTAG).
• Internal Processor Registers (IPRs): Provides information on various IPRs for controlling and monitoring the Ibox, Mbox, Cbox, and PALcode.
• PALcode: Explains the Privileged Architecture Library code, which provides OS-specific primitives for context switching, interrupts, exceptions, and memory management.
• Electrical and Thermal Data: Includes absolute maximum ratings, DC/AC electrical characteristics, clocking schemes, power supply considerations (including decoupling and sequencing), and thermal management guidelines (operating temperature, heat sink specifications).

In essence, the document serves as a comprehensive technical reference for designing systems around the Alpha 21164 microprocessor.