DECchip 21071 and DECchip 21072

This document is a detailed Data Sheet for the DECchip 21071 and DECchip 21072 Core Logic Chipsets, produced by Digital Equipment Corporation. It serves as a comprehensive technical reference for engineers designing uniprocessor systems based on the Alpha AXP 21064 microprocessor.

The chipsets provide a cost-effective solution by integrating essential system functions, including a secondary cache (Bcache), memory controller, PCI interface, and associated data path functions, minimizing the need for discrete logic.

Key Features and Components:

• Alpha AXP 21064 Support: Designed to work with the entire family of DECchip 21064 microprocessors.
• System Clock Frequency: Operates at up to 33 MHz.

• Memory Configuration:

  • DECchip 21071: Supports 128-bit cache and 64-bit memory.
  • DECchip 21072: Supports 128-bit cache and 128-bit memory, including 32-bit parity/ECC on Bcache and memory data.

• Bcache/Memory Controller: Features a write-back cache (128 KB to 16 MB, using 17 ns SRAMs or faster), supports 8 MB to 4 GB of main memory via industry-standard SIMMs, and includes a DRAM controller with fully programmable timing (15 ns granularity). It provides high CPU bandwidths (267 MB/s write, 107 MB/s read).

• High-Performance PCI Bridge: Offers 32-bit multiplexed address/data, industry-standard compliance with no glue logic required for PCI-compliant chips. It supports high DMA bandwidths (120 MB/s write, 70 MB/s read) and programmed I/O bandwidths (82 MB/s write, 22 MB/s read), along with scatter/gather map support.
• Graphics Support: Includes a high-bandwidth memory data path to Video RAM (VRAM) and provides direct connection support for VRAM frame buffers.

The chipset is comprised of three unique 208-pin PQFP gate arrays:

• DECchip 21071-CA: The Cache/Memory Controller.
• DECchip 21071-DA: The PCI Interface (bridge).
• DECchip 21071-BA: The Data Path component, responsible for bus widths, buffering, and error checking/correction logic.

The document is divided into sections detailing the pin descriptions, architectural overviews, programmer's references (registers, address translation), transaction flows, electrical data, and power-up/initialization for each of the three chipset components.