Digital Semiconductor Alpha 21064 and 21064A Microprocessors Hardware Reference Manual

This document, the "Digital Semiconductor Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference Manual," is a comprehensive technical guide for system designers integrating these microprocessors. It provides detailed hardware information, operational characteristics, and design considerations for various models, including the 21064-150, 21064-166, 21064-200, and 21064A-200, 21064A-233, 21064A-275, 21064A-275-PC, and 21064A-300. The manual supersedes previous versions and explicitly highlights differences between the 21064 and 21064A models.

Key areas covered include:

1. Introduction and Architecture Overview: Introduces the Alpha architecture as a 64-bit load/store RISC design emphasizing speed, multiple instruction issue, and multi-processor support. It highlights key features of the 21064/21064A chips, such as their CMOS superscalar, super-pipelined design with dual instruction issue, on-chip caches (8KB for 21064, 16KB for 21064A), integrated floating-point units, and memory management units (ITB, DTB). It also details the distinct parity and ECC support for each model (21064: data bus; 21064A: Icache, Dcache, and data bus).
2. Internal Architecture: Explores the functional units of the microprocessors:
   • Ibox (Instruction Box): Manages instruction fetching, decoding, issuing, pipeline control, branch prediction (with distinct logic for 21064 vs. 21064A), instruction translation buffers (ITBs), interrupt logic, and performance counters.
   • Ebox (Execution Box): Handles 64-bit integer operations.
   • Abox (Address Box): Manages address generation, load/store operations, the Data Translation Buffer (DTB), write buffer, and the Bus Interface Unit (BIU).
   • Fbox (Floating-Point Box): Processes VAX and IEEE floating-point instructions, including specific inexact flag behavior differences between 21064 and 21064A.
   • Pipeline Organization: Details the seven-stage pipeline for integer and memory operations and the ten-stage pipeline for floating-point operations, along with scheduling and dual-issue rules.
3. Instruction Set: Summarizes the Alpha architecture instruction set, including IEEE and VAX floating-point instructions, and lists opcodes reserved for PALcode and Digital.
4. Privileged Architecture Library Code (PALcode): Describes PALcode as chip-specific subroutines providing operating system primitives (e.g., context switching, memory management, interrupt handling). It explains PALmode, a special environment where these routines execute with privileged access, and details the specific hardware-level instructions (HW_MFPR, HW_MTPR, HW_LD, HW_ST, HW_REI) used within PALcode.
5. Internal Processor Registers (IPRs): Provides detailed descriptions and formats for various IPRs within the Ibox and Abox, such as translation buffers, cache control registers, exception address registers, interrupt request/enable registers, memory management control registers, and cycle counters.
6. External Interface: Covers the physical interface of the microprocessors, including:
   • Signal Names and Functions: Descriptions of data, address, and parity/ECC buses, external cache control signals, interrupts, and clock signals.
   • Bus Transactions: Details on reset procedures, fast external cache reads/writes, block transactions (READ_BLOCK, WRITE_BLOCK), load-locked/store-conditional transactions, and memory barriers.
   • Hardware Error Handling: Discusses mechanisms for detecting and handling single-bit and double-bit ECC/parity errors in caches and the Bus Interface Unit.
7. Electrical Data: Presents absolute maximum ratings, DC and AC electrical characteristics, power supply requirements (3.3V nominal with 5V tolerant inputs and specific sequencing requirements), and detailed timing diagrams for external cycles and clock signals.
8. Thermal Management: Provides critical parameters for thermal design, including thermal device characteristics (junction-to-case, case-to-ambient thermal resistance), power dissipation calculations for different models and frequencies, and techniques for forced-air cooling and heat sink design.
9. Signal Integrity: Addresses issues critical for robust design, such as power supply decoupling, reference voltage (vRef), I/O driver characteristics (VI curves, switching characteristics), and input clock termination.
10. Mechanical Data and Packaging: Includes physical dimensions of the microprocessor packages (431-pin PGA) and comprehensive pin lists for all signals.

Overall, the document serves as an essential technical reference for engineers designing systems based on Digital's Alpha 21064 and 21064A microprocessors, covering everything from core architecture and instruction sets to detailed electrical, thermal, and mechanical specifications.