DECchip 21064 Evaluation Board User's Guide

This document is the User's Guide for the DECchip 21064 Evaluation Board (EB64), published by Digital Equipment Corporation in September 1993. It serves as a comprehensive guide for system designers and others involved in designing or evaluating computing systems based on the DECchip 21064 microprocessor, which implements the Alpha AXP architecture.

The guide provides a detailed description of the EB64's features, configuration, and functional operation. Key aspects covered include:

• Components: The board features a 150 MHz DECchip 21064 CPU, a Dynamic RAM (DRAM) main memory subsystem (4 to 64 Mbytes), a 512 Kbyte external backup cache (Bcache) using SRAMs, and an ISA interface.
• Integrated Devices: The ISA interface is managed by a VLSI Technology SC486 chip, offering bus control, DMA, interrupt control, timers, RTC, mouse, and keyboard support. It also includes slow-speed peripheral devices (serial ports, floppy disk controller via an FDC37C651 chip) and an Ethernet port (AMD Am79C960 PCnet-ISA).
• ROMs: Dedicated Debug ROMs and a Serial ROM (SROM) for initialization and debug capabilities.
• Functional Description: Detailed explanations of the board's 34-bit address space partitioning (memory and I/O), memory subsystem cycles (DRAM and Bcache), I/O subsystem operations, power requirements, and system clocking.
• Expansion Interface: A significant section dedicated to the high-speed, buffered 21064 pin-bus expansion interface, allowing users to design and connect custom hardware. It addresses design considerations like data path width and cache coherency.
• Uses: The EB64 is positioned as a single-board platform for system development, software debugging, memory/Bcache subsystem evaluation, and I/O device development.
• Support: The guide also provides information on technical support and how to order associated literature and DECchip products.