The Stanford University Design System Overview

The Stanford University Design System (SUDS) is a comprehensive Computer-Aided Design (CAD) system developed at Stanford, primarily for designing circuit schematics and logic. It serves as a central database for electronic design, generating digital data files that streamline the process and reduce design time and cost compared to manual methods.

Key Features and Workflow:

1. Schematic Capture: Engineers, technicians, or draftspersons input rough circuit sketches into SUDS using its interactive drawing program (GCD), converting them into formal schematics.
2. Libraries: SUDS utilizes two main libraries: .DRW for graphic symbols (e.g., electrical components, flow chart symbols) and DIPS.DIP for their corresponding electrical characteristics. These libraries ensure accurate representation and enable automated validation.
3. Data Generation (Wirelister): A core component, the Wirelister, processes the schematic data to automatically generate various outputs:
   • Wirelists (WL, WLU, WLS): Detailed lists of net runs, component/pin utilization, and summaries highlighting documentation or logic errors.
   • Parts Lists (PRT): Comprehensive lists of all components used in the design.
   • Input for other CAD tools: Connection files (.CON, .TLE) that feed directly into automated Printed Circuit Board (PCB) layout systems like CALDEC and IDEA.
4. Design Aids and Verification: SUDS integrates with or generates input for crucial design analysis tools:
   • Logic Simulation (SAGE 2): To verify the logical functionality of the design before physical layout.
   • Placement Optimization: To determine the most efficient physical arrangement of circuit elements.
   • Delay Calculation: To analyze signal propagation times within the circuit.
   • Manufacturing Outputs: Generates data for manufacturing processes such as wirewrap, multiwire, and KPL (a system for generating parts information), eliminating manual data translation.
5. Design Iteration and Consistency: SUDS facilitates a continuous design loop. Changes made during the physical layout phase (e.g., in CALDEC or IDEA) can be fed back into SUDS to update the original design files, ensuring the schematic data remains consistent with the physical board layout.

Benefits:

SUDS significantly reduces human error, automates tedious manual tasks like re-drawing and data re-translation, and improves the overall accuracy and consistency of design documentation. By producing computer-readable data files, it enables faster turnaround times for design iterations and engineering change orders (ECOs), making complex electronic design processes more efficient and feasible.

The system operates on DECsystem 10 or 20 operating systems, utilizing programmable graphics processors as user workstations.