dtj v06-01 1994

This Winter 1994 issue of the Digital Technical Journal focuses on three key areas of innovation at Digital Equipment Corporation: high-performance networking, OpenVMS AXP system software, and Alpha AXP PC hardware.

Here's a breakdown of the main topics covered:

1. GIGAswitch System: A High-performance Packet-switching Platform:

   • Overview: Describes the GIGAswitch system, a multiport packet-switching platform utilizing a 36-port, 100 Mb/s crossbar switching fabric. It achieves high performance through distributed forwarding hardware and custom VLSI chips, capable of 6.25 million connections per second.
   • Key Design Issues: Discusses data link independence, a "take-a-ticket" arbitration algorithm for crossbar output ports, "hunt groups" for dynamic traffic distribution, and an optimized hash algorithm for address lookups (critical for FDDI at 440,000 packets/sec/port). It also details packet buffering using multiple FIFO queues to mitigate head-of-line blocking and robust design for overload conditions, including hardware and software cooperation for guaranteed packet reception.
   • Implementation: The first product built on this platform is a 22-port IEEE 802.1d FDDI bridge, which achieves forwarding rates over 200,000 packets per second per port with a latency of approximately 14 microseconds.

2. OpenVMS AXP System Software Enhancements:

   • Performance of DEC Rdb Version 6.0 on AXP Systems:
     • Challenge: Addresses the "I/O bottleneck" on Alpha AXP systems where CPU speed significantly outpaces disk I/O latency.
     • Solutions: Implemented enhancements to minimize I/O operations and reduce stall times. Key features include careful data alignment, use of "global buffers" to reduce read I/O, asynchronous prefetch (APF) for read requests, asynchronous batch writes (ABWs) to reduce write stall times, and an AIJ (After Image Journal) log server (ALS) with an electronic disk cache (ACE) to accelerate transaction commits. It also improved sorting mechanisms with an optimized quicksort algorithm.
     • Results: Achieved world-record TPC-A transaction rates (327.99 TPS on single AXP CPU, 527.73 TPS on dual AXP CPU), demonstrating significant performance gains.
   • Improving Process to Increase Productivity While Assuring Quality: A Case Study of the Volume Shadowing Port to OpenVMS AXP:
     • Context: Details the rapid porting of Volume Shadowing Phase II (a data replication feature for availability) to OpenVMS AXP under tight schedules and resource constraints.
     • Process Innovations: The team reshaped its software development process by incorporating formal inspections (for early defect detection), rigorous profile testing (risk-directed, using orthogonal arrays for efficient test coverage), and clear release criteria with defect tracking.
     • Outcome: The approach led to a high-quality product delivered ahead of schedule, significant cost-effectiveness in defect removal (68% of defects found during low-cost inspections), and improved productivity.

3. Alpha AXP PC Hardware:

   • The Evolution of the Alpha AXP PC:
     • Journey: Traces the development of low-cost Alpha AXP personal computers through experimental systems: Beta (demonstrated feasibility of using the DECchip 21064 with industry-standard PC components), Theta (incorporated the EISA bus, highlighting challenges with industry standards), and finally the DECPC AXP 150 product.
     • Lessons Learned: Emphasizes that combining Alpha AXP microprocessors with PC components is feasible, evolutionary design is effective, careful attention is needed for Intel-designed bus interfaces, and addressing quality, test, and assembly issues early in the design cycle is crucial.
   • Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip:
     • Innovation: Introduces the DECchip 21066, the first Alpha AXP microprocessor designed for cost-focused system applications like PCs and desktops.
     • Integration: Integrates a high-performance, superscalar CPU core with significant system functions on a single chip, including a high-bandwidth memory controller, an industry-standard PCI I/O controller, graphics-assisting hardware, internal caches, and an on-chip phase-locked loop (PLL).
     • Design Philosophy: Aims to reduce overall system cost and shorten time-to-market through functional integration and design choices that ease system implementation (e.g., 64-bit data bus, programmable memory timing, ECC, graphics-assist logic).
     • Verification: Highlights the use of a pseudorandom design exerciser and shared memory testing to ensure correctness and reliability.
     • Impact: Positioned to provide Pentium-class performance at a competitive price, making Alpha AXP more accessible for various applications.