Semiconductor Technologies

This Digital Technical Journal, Volume 4, Number 2, Spring 1992, is dedicated to Semiconductor Technologies at Digital Equipment Corporation (DEC). The primary focus is on the development and manufacturing of CMOS-4 technology, which enabled DEC to produce leading-edge microprocessors like the Alpha 21064 (the world's fastest at the time) and NVAX.

The document highlights DEC's strategic goal of achieving leadership in microprocessor performance by adopting a "concurrent" approach, closely linking chip design with process development. This involved aggressive scaling, aiming to double gate density and increase gate speed by 30% with each new CMOS generation, while also growing chip area by 40%.

Key themes and advancements discussed in the journal include:

1. Microprocessor Performance and CMOS Technologies: Details the scaling methodology that reduced feature sizes (to 0.75 µm in CMOS-4), improved gate density and speed, and allowed for increased on-chip cache memory and pipelining, significantly boosting performance (e.g., 4.8x SPECmark improvement from CMOS-2 to CMOS-4). The shift to a 3.3V power supply is also discussed for power dissipation management.

2. Numerical Device and Process Simulation Tools: Explores the fundamental role of simulation programs (like MINIMOS, SUPREM3, and PROMIS) in transistor design and characterization. It covers physical models for ion implantation, diffusion, and mobility, and numerical methods for enhancing simulator performance and accuracy. These tools provided crucial insights, reducing fabrication time and cost.

3. CMOS-4 Front-End Process Development: Focuses on the formation of logic gates and dense on-chip memory. This includes the development of symmetric n+ and p+ doped polysilicon transistors with low threshold voltage, shallow medium doped drain (MDD) junctions for hot carrier protection, and the integration of self-aligned cobalt silicide (CoSi2) for low resistance. The use of a titanium-nitride (TiN) local interconnect scheme for high-density SRAM cells (100 µm²) is also highlighted.

4. CMOS-4 Back-End Process Development: Describes the creation of the 0.75 µm triple-level aluminum alloy metallization, crucial for high circuit density and performance. It covers modifications to existing photolithography, plasma etch, and PVD metallization tools for submicron requirements, and the introduction of blanket CVD tungsten plugs for contacts and vias, along with plasma-enhanced TEOS oxide planarization processes to manage challenging aspect ratios and ensure reliable interconnects.

5. Defect Reduction and Yield Enhancement: Outlines strategies implemented in VLSI manufacturing to achieve high product yields. This encompasses rigorous microcontamination control (clean room air, ultrapure water, chemicals), improvements in wafer handling and monitoring, and a comprehensive yield enhancement methodology. This methodology utilizes test chips, yield models (negative binomial), and defect analysis (e.g., p-gate leakage, metal 2 short circuits) to identify and prioritize defect sources for continuous improvement.

6. Reliability Assurance (Hot Carrier and Electromigration):

   • Transistor Hot Carrier Reliability: Presents a physically-based method to predict and assure transistor lifetime, accounting for different types of hot carrier-induced degradation and manufacturing variations.
   • Electromigration Reliability: Discusses the mass transport phenomena in metal interconnects due to electron conduction. A scaling model and testing methodologies are presented to characterize and assure the long-term reliability of VLSI interconnects, including the impact of tungsten-filled vias.

In essence, the journal demonstrates how DEC's integrated approach to chip design, process development, and rigorous manufacturing control, underpinned by advanced simulation and reliability engineering, was critical in delivering the high-performance microprocessors of the early 1990s.